This invention relates to a semiconductor integrated circuit device and a method of arranging a functional cell, and in particular, a semiconductor integrated circuit device, such as, a gate array on which a logic circuit of super speed operation consisting of CML (Current Mode Logic) is placed and a method of arranging a functional cell.
In a semiconductor integrated circuit device of the type described, impedance of a metal wiring line or pattern can not be ignored in a digital signal process of super high frequency exceeding 600 MHz, such as, timing design.
The logic circuit for processing the digital signal of super high frequency is represented by CML (Current Mode logic). In this event, the CML is composed of a differential amplifier. With such a structure, an input and an output interface with complementary signals of positive phase and negative (or opposite) phase corresponding to an input and an output of the differential amplifier.
In a gate array on which the CML is placed as the logic circuit, there is a difference of impedance caused by a difference of wiring line lengths between signals of the positive phase and the negative phase as the complementary signals between functional cells. In consequence, it is difficult to optimally perform the timing design because the both outputs are unbalanced.
In a conventional semiconductor integrated circuit device of the type described, the wiring line lengths are completed between the positive phase and the negative phase. In particular, with respect to a critical signal path, the functional cell is preferentially forced to be arranged in advance. Further, the wiring line path connected after automatic arranging and wiring process is suitably changed.
Moreover, an arranging position of the functional cell is also changed. Thereby, a balanced arrangement is realized in the conventional semiconductor integrated circuit device.
In the above-mentioned semiconductor integrated circuit device and the method of arranging the functional cell, the position is not always kept to a minimum distance between an output terminal of the functional cell of previous stage and an input terminal of the functional cell of next stage.
Thereby, the impedance difference takes place because the lengths of signal wiring lines of the positive phase and the negative phase of the CML are different from each other.
In this condition, when both lengths of the signal wiring lines are completed to balance both signals, a redundant wiring line must be added to a shorter wiring line to correspond with a length of a longer wiring line. In this case, a delay becomes large because of the redundant wiring line length, and timing margin and power are largely increased.
Further, it is impossible to complete the signal wiring line lengths of the positive phase and the negative phase in only the automatic wiring process. When the difference between the both lengths exceeds an allowable range in the timing design, the wiring line path and the arranging position of the functional cell are manually changed after the automatic wiring process. Consequently, a long time is necessary to converge timing verification.
As a result, design TAT (Turn Around Time) is inevitably increased by the automatic wiring process and correction of the arranging position of the functional cell.